



/*  metrowerks sample code  */



#ifndef	_56805_H
#define _56805_H

/* On-Chip Core Configuration Registers */
#define OPGDBR		0xffff
#define IPR			0xfffb
#define BCR			0xfff9


/* System Integration Module (SIM) */
#define SYS_BASE	0x0C00

#define SYS_CTRL	SYS_BASE + 0x0
#define SYS_STS		SYS_BASE + 0x1
#define MSH_ID		SYS_BASE + 0x6
#define LSH_ID		SYS_BASE + 0x7
#define TST_REG0	SYS_BASE + 0x18
#define TST_REG1	SYS_BASE + 0x19
#define TST_REG2	SYS_BASE + 0x1a
#define TST_REG3	SYS_BASE + 0x1b
#define TST_REG4	SYS_BASE + 0x1c


/* Quad timer */
#define TMRA_BASE	0x0d00

#define TMRA0_CMP1		TMRA_BASE + 0x0
#define TMRA0_CMP2		TMRA_BASE + 0x1
#define TMRA0_CAP		TMRA_BASE + 0x2
#define TMRA0_LOAD		TMRA_BASE + 0x3
#define TMRA0_HOLD		TMRA_BASE + 0x4
#define TMRA0_CNTR		TMRA_BASE + 0x5
#define TMRA0_CTRL		TMRA_BASE + 0x6
#define TMRA0_SCR		TMRA_BASE + 0x7

#define TMRA1_CMP1		TMRA_BASE + 0x8
#define TMRA1_CMP2		TMRA_BASE + 0x9
#define TMRA1_CAP		TMRA_BASE + 0xa
#define TMRA1_LOAD		TMRA_BASE + 0xb
#define TMRA1_HOLD		TMRA_BASE + 0xc
#define TMRA1_CNTR		TMRA_BASE + 0xd
#define TMRA1_CTRL		TMRA_BASE + 0xe
#define TMRA1_SCR		TMRA_BASE + 0xf

#define TMRA2_CMP1		TMRA_BASE + 0x10
#define TMRA2_CMP2		TMRA_BASE + 0x11
#define TMRA2_CAP		TMRA_BASE + 0x12
#define TMRA2_LOAD		TMRA_BASE + 0x13
#define TMRA2_HOLD		TMRA_BASE + 0x14
#define TMRA2_CNTR		TMRA_BASE + 0x15
#define TMRA2_CTRL		TMRA_BASE + 0x16
#define TMRA2_SCR		TMRA_BASE + 0x17

#define TMRA3_CMP1		TMRA_BASE + 0x18
#define TMRA3_CMP2		TMRA_BASE + 0x19
#define TMRA3_CAP		TMRA_BASE + 0x1a
#define TMRA3_LOAD		TMRA_BASE + 0x1b
#define TMRA3_HOLD		TMRA_BASE + 0x1c
#define TMRA3_CNTR		TMRA_BASE + 0x1d
#define TMRA3_CTRL		TMRA_BASE + 0x1e
#define TMRA3_SCR		TMRA_BASE + 0x1f


#define TMRB_BASE	0x0d20

#define TMRB0_CMP1		TMRB_BASE + 0x0
#define TMRB0_CMP2		TMRB_BASE + 0x1
#define TMRB0_CAP		TMRB_BASE + 0x2
#define TMRB0_LOAD		TMRB_BASE + 0x3
#define TMRB0_HOLD		TMRB_BASE + 0x4
#define TMRB0_CNTR		TMRB_BASE + 0x5
#define TMRB0_CTRL		TMRB_BASE + 0x6
#define TMRB0_SCR		TMRB_BASE + 0x7

#define TMRB1_CMP1		TMRB_BASE + 0x8
#define TMRB1_CMP2		TMRB_BASE + 0x9
#define TMRB1_CAP		TMRB_BASE + 0xa
#define TMRB1_LOAD		TMRB_BASE + 0xb
#define TMRB1_HOLD		TMRB_BASE + 0xc
#define TMRB1_CNTR		TMRB_BASE + 0xd
#define TMRB1_CTRL		TMRB_BASE + 0xe
#define TMRB1_SCR		TMRB_BASE + 0xf

#define TMRB2_CMP1		TMRB_BASE + 0x10
#define TMRB2_CMP2		TMRB_BASE + 0x11
#define TMRB2_CAP		TMRB_BASE + 0x12
#define TMRB2_LOAD		TMRB_BASE + 0x13
#define TMRB2_HOLD		TMRB_BASE + 0x14
#define TMRB2_CNTR		TMRB_BASE + 0x15
#define TMRB2_CTRL		TMRB_BASE + 0x16
#define TMRB2_SCR		TMRB_BASE + 0x17

#define TMRB3_CMP1		TMRB_BASE + 0x18
#define TMRB3_CMP2		TMRB_BASE + 0x19
#define TMRB3_CAP		TMRB_BASE + 0x1a
#define TMRB3_LOAD		TMRB_BASE + 0x1b
#define TMRB3_HOLD		TMRB_BASE + 0x1c
#define TMRB3_CNTR		TMRB_BASE + 0x1d
#define TMRB3_CTRL		TMRB_BASE + 0x1e
#define TMRB3_SCR		TMRB_BASE + 0x1f


#define TMRC_BASE	0x0d40

#define TMRC0_CMP1		TMRC_BASE + 0x0
#define TMRC0_CMP2		TMRC_BASE + 0x1
#define TMRC0_CAP		TMRC_BASE + 0x2
#define TMRC0_LOAD		TMRC_BASE + 0x3
#define TMRC0_HOLD		TMRC_BASE + 0x4
#define TMRC0_CNTR		TMRC_BASE + 0x5
#define TMRC0_CTRL		TMRC_BASE + 0x6
#define TMRC0_SCR		TMRC_BASE + 0x7

#define TMRC1_CMP1		TMRC_BASE + 0x8
#define TMRC1_CMP2		TMRC_BASE + 0x9
#define TMRC1_CAP		TMRC_BASE + 0xa
#define TMRC1_LOAD		TMRC_BASE + 0xb
#define TMRC1_HOLD		TMRC_BASE + 0xc
#define TMRC1_CNTR		TMRC_BASE + 0xd
#define TMRC1_CTRL		TMRC_BASE + 0xe
#define TMRC1_SCR		TMRC_BASE + 0xf

#define TMRC2_CMP1		TMRC_BASE + 0x10
#define TMRC2_CMP2		TMRC_BASE + 0x11
#define TMRC2_CAP		TMRC_BASE + 0x12
#define TMRC2_LOAD		TMRC_BASE + 0x13
#define TMRC2_HOLD		TMRC_BASE + 0x14
#define TMRC2_CNTR		TMRC_BASE + 0x15
#define TMRC2_CTRL		TMRC_BASE + 0x16
#define TMRC2_SCR		TMRC_BASE + 0x17

#define TMRC3_CMP1		TMRC_BASE + 0x18
#define TMRC3_CMP2		TMRC_BASE + 0x19
#define TMRC3_CAP		TMRC_BASE + 0x1a
#define TMRC3_LOAD		TMRC_BASE + 0x1b
#define TMRC3_HOLD		TMRC_BASE + 0x1c
#define TMRC3_CNTR		TMRC_BASE + 0x1d
#define TMRC3_CTRL		TMRC_BASE + 0x1e
#define TMRC3_SCR		TMRC_BASE + 0x1f


#define TMRD_BASE	0x0d60

#define TMRD0_CMP1		TMRD_BASE + 0x0
#define TMRD0_CMP2		TMRD_BASE + 0x1
#define TMRD0_CAP		TMRD_BASE + 0x2
#define TMRD0_LOAD		TMRD_BASE + 0x3
#define TMRD0_HOLD		TMRD_BASE + 0x4
#define TMRD0_CNTR		TMRD_BASE + 0x5
#define TMRD0_CTRL		TMRD_BASE + 0x6
#define TMRD0_SCR		TMRD_BASE + 0x7

#define TMRD1_CMP1		TMRD_BASE + 0x8
#define TMRD1_CMP2		TMRD_BASE + 0x9
#define TMRD1_CAP		TMRD_BASE + 0xa
#define TMRD1_LOAD		TMRD_BASE + 0xb
#define TMRD1_HOLD		TMRD_BASE + 0xc
#define TMRD1_CNTR		TMRD_BASE + 0xd
#define TMRD1_CTRL		TMRD_BASE + 0xe
#define TMRD1_SCR		TMRD_BASE + 0xf

#define TMRD2_CMP1		TMRD_BASE + 0x10
#define TMRD2_CMP2		TMRD_BASE + 0x11
#define TMRD2_CAP		TMRD_BASE + 0x12
#define TMRD2_LOAD		TMRD_BASE + 0x13
#define TMRD2_HOLD		TMRD_BASE + 0x14
#define TMRD2_CNTR		TMRD_BASE + 0x15
#define TMRD2_CTRL		TMRD_BASE + 0x16
#define TMRD2_SCR		TMRD_BASE + 0x17

#define TMRD3_CMP1		TMRD_BASE + 0x18
#define TMRD3_CMP2		TMRD_BASE + 0x19
#define TMRD3_CAP		TMRD_BASE + 0x1a
#define TMRD3_LOAD		TMRD_BASE + 0x1b
#define TMRD3_HOLD		TMRD_BASE + 0x1c
#define TMRD3_CNTR		TMRD_BASE + 0x1d
#define TMRD3_CTRL		TMRD_BASE + 0x1e
#define TMRD3_SCR		TMRD_BASE + 0x1f


/* Controller Area Network (CAN) */
#define CAN_BASE	0x0d80

#define CANCTL0			CAN_BASE + 0x0
#define CANCTL1			CAN_BASE + 0x1
#define CANBTR0			CAN_BASE + 0x2
#define CANBR1			CAN_BASE + 0x3
#define CANRFLG			CAN_BASE + 0x4
#define CANRIER			CAN_BASE + 0x5
#define CANTFLG			CAN_BASE + 0x6
#define CANTCR			CAN_BASE + 0x7
#define CANIDAC			CAN_BASE + 0x8
#define CANRXERR		CAN_BASE + 0xe
#define CANTXERR		CAN_BASE + 0xf
#define CANIDAR0		CAN_BASE + 0x10
#define CANIDAR1		CAN_BASE + 0x11
#define CANIDAR2		CAN_BASE + 0x12
#define CANIDAR3		CAN_BASE + 0x13
#define CANIDAR4		CAN_BASE + 0x18
#define CANIDAR5		CAN_BASE + 0x19
#define CANIDAR6		CAN_BASE + 0x1a
#define CANIDAR7		CAN_BASE + 0x1b
#define CANIDMR0		CAN_BASE + 0x14
#define CANIDMR1		CAN_BASE + 0x15
#define CANIDMR2		CAN_BASE + 0x16
#define CANIDMR3		CAN_BASE + 0x17
#define CANIDMR4		CAN_BASE + 0x1c
#define CANIDMR5		CAN_BASE + 0x1d
#define CANIDMR6		CAN_BASE + 0x1e
#define CANIDMR7		CAN_BASE + 0x1f
#define CAN_RB_IDR0		CAN_BASE + 0x40
#define CAN_RB_IDR1		CAN_BASE + 0x41
#define CAN_RB_IDR2		CAN_BASE + 0x42
#define CAN_RB_IDR3		CAN_BASE + 0x43
#define CAN_RB_DSR0		CAN_BASE + 0x44
#define CAN_RB_DSR1		CAN_BASE + 0x45
#define CAN_RB_DSR2		CAN_BASE + 0x46
#define CAN_RB_DSR3		CAN_BASE + 0x47
#define CAN_RB_DSR4		CAN_BASE + 0x48
#define CAN_RB_DSR5		CAN_BASE + 0x49
#define CAN_RB_DSR6		CAN_BASE + 0x4a
#define CAN_RB_DSR7		CAN_BASE + 0x4b
#define CAN_RB_DLR		CAN_BASE + 0x4c
#define CAN_RB_TBPR		CAN_BASE + 0x4d
#define CAN_TB0_IDR0	CAN_BASE + 0x50
#define CAN_TB0_IDR1	CAN_BASE + 0x51
#define CAN_TB0_IDR2	CAN_BASE + 0x52
#define CAN_TB0_IDR3	CAN_BASE + 0x53
#define CAN_TB0_DSR0	CAN_BASE + 0x54
#define CAN_TB0_DSR1	CAN_BASE + 0x55
#define CAN_TB0_DSR2	CAN_BASE + 0x56
#define CAN_TB0_DSR3	CAN_BASE + 0x57
#define CAN_TB0_DSR4	CAN_BASE + 0x58
#define CAN_TB0_DSR5	CAN_BASE + 0x59
#define CAN_TB0_DSR6	CAN_BASE + 0x5a
#define CAN_TB0_DSR7	CAN_BASE + 0x5b
#define CAN_TB0_DLR		CAN_BASE + 0x5c
#define CAN_TB0_TBPR	CAN_BASE + 0x5d
#define CAN_TB1_IDR0	CAN_BASE + 0x60
#define CAN_TB1_IDR1	CAN_BASE + 0x61
#define CAN_TB1_IDR2	CAN_BASE + 0x62
#define CAN_TB1_IDR3	CAN_BASE + 0x63
#define CAN_TB1_DSR0	CAN_BASE + 0x64
#define CAN_TB1_DSR1	CAN_BASE + 0x65
#define CAN_TB1_DSR2	CAN_BASE + 0x66
#define CAN_TB1_DSR3	CAN_BASE + 0x67
#define CAN_TB1_DSR4	CAN_BASE + 0x68
#define CAN_TB1_DSR5	CAN_BASE + 0x69
#define CAN_TB1_DSR6	CAN_BASE + 0x6a
#define CAN_TB1_DSR7	CAN_BASE + 0x6b
#define CAN_TB1_DLR		CAN_BASE + 0x6c
#define CAN_TB1_TBPR	CAN_BASE + 0x6d
#define CAN_TB2_IDR0	CAN_BASE + 0x70
#define CAN_TB2_IDR1	CAN_BASE + 0x71
#define CAN_TB2_IDR2	CAN_BASE + 0x72
#define CAN_TB2_IDR3	CAN_BASE + 0x73
#define CAN_TB2_DSR0	CAN_BASE + 0x74
#define CAN_TB2_DSR1	CAN_BASE + 0x75
#define CAN_TB2_DSR2	CAN_BASE + 0x76
#define CAN_TB2_DSR3	CAN_BASE + 0x77
#define CAN_TB2_DSR4	CAN_BASE + 0x78
#define CAN_TB2_DSR5	CAN_BASE + 0x79
#define CAN_TB2_DSR6	CAN_BASE + 0x7a
#define CAN_TB2_DSR7	CAN_BASE + 0x7b
#define CAN_TB2_DLR		CAN_BASE + 0x7c
#define CAN_TB2_TBPR	CAN_BASE + 0x7d


/* Pulse Width Modulator Module (PWM) */
#define PWMA_BASE	0x0e00

#define PWMA_PMCTL		PWMA_BASE + 0x0
#define PWMA_PMFCTL		PWMA_BASE + 0x1
#define PWMA_PMFSA		PWMA_BASE + 0x2
#define PWMA_PMOUT		PWMA_BASE + 0x3
#define PWMA_PMCNT		PWMA_BASE + 0x4
#define PWMA_PWMCM		PWMA_BASE + 0x5
#define PWMA_PWMVAL0	PWMA_BASE + 0x6
#define PWMA_PWMVAL1	PWMA_BASE + 0x7
#define PWMA_PWMVAL2	PWMA_BASE + 0x8
#define PWMA_PWMVAL3	PWMA_BASE + 0x9
#define PWMA_PWMVAL4	PWMA_BASE + 0xa
#define PWMA_PWMVAL5	PWMA_BASE + 0xb
#define PWMA_PMDEADTM	PWMA_BASE + 0xc
#define PWMA_PMDISMAP1	PWMA_BASE + 0xd
#define PWMA_PMDISMAP2	PWMA_BASE + 0xe
#define PWMA_PMDCFG		PWMA_BASE + 0xf
#define PWMA_PMCCR		PWMA_BASE + 0x10
#define PWMA_PMPORT		PWMA_BASE + 0x11

#define PWMB_BASE	0x0e20

#define PWMB_PMCTL		PWMB_BASE + 0x0
#define PWMB_PMFCTL		PWMB_BASE + 0x1
#define PWMB_PMFSA		PWMB_BASE + 0x2
#define PWMB_PMOUT		PWMB_BASE + 0x3
#define PWMB_PMCNT		PWMB_BASE + 0x4
#define PWMB_PWMCM		PWMB_BASE + 0x5
#define PWMB_PWMVAL0	PWMB_BASE + 0x6
#define PWMB_PWMVAL1	PWMB_BASE + 0x7
#define PWMB_PWMVAL2	PWMB_BASE + 0x8
#define PWMB_PWMVAL3	PWMB_BASE + 0x9
#define PWMB_PWMVAL4	PWMB_BASE + 0xa
#define PWMB_PWMVAL5	PWMB_BASE + 0xb
#define PWMB_PMDEADTM	PWMB_BASE + 0xc
#define PWMB_PMDISMAP1	PWMB_BASE + 0xd
#define PWMB_PMDISMAP2	PWMB_BASE + 0xe
#define PWMB_PMDCFG		PWMB_BASE + 0xf
#define PWMB_PMCCR		PWMB_BASE + 0x10
#define PWMB_PMPORT		PWMB_BASE + 0x11

/* Quadrature Decoder */
#define DEC0_BASE	0x0e40

#define QD0_DECCR	DEC0_BASE + 0x0
#define QD0_FIR		DEC0_BASE + 0x1
#define QD0_WTR		DEC0_BASE + 0x2
#define QD0_POSD	DEC0_BASE + 0x3
#define QD0_POSDH	DEC0_BASE + 0x4
#define QD0_REV		DEC0_BASE + 0x5
#define QD0_REVH	DEC0_BASE + 0x6
#define QD0_UPOS	DEC0_BASE + 0x7
#define QD0_LPOS	DEC0_BASE + 0x8
#define QD0_UPOSH	DEC0_BASE + 0x9
#define QD0_LPOSH	DEC0_BASE + 0xa
#define QD0_UIR		DEC0_BASE + 0xb
#define QD0_LIR		DEC0_BASE + 0xc
#define QD0_IMR		DEC0_BASE + 0xd
#define QD0_TSTREG	DEC0_BASE + 0xe

#define DEC1_BASE	0x0e50

#define QD1_DECCR	DEC1_BASE + 0x0
#define QD1_FIR		DEC1_BASE + 0x1
#define QD1_WTR		DEC1_BASE + 0x2
#define QD1_POSD	DEC1_BASE + 0x3
#define QD1_POSDH	DEC1_BASE + 0x4
#define QD1_REV		DEC1_BASE + 0x5
#define QD1_REVH	DEC1_BASE + 0x6
#define QD1_UPOS	DEC1_BASE + 0x7
#define QD1_LPOS	DEC1_BASE + 0x8
#define QD1_UPOSH	DEC1_BASE + 0x9
#define QD1_LPOSH	DEC1_BASE + 0xa
#define QD1_UIR		DEC1_BASE + 0xb
#define QD1_LIR		DEC1_BASE + 0xc
#define QD1_IMR		DEC1_BASE + 0xd
#define QD1_TSTREG	DEC1_BASE + 0xe


/* Interrupt controller */
#define ITCN_BASE	0x0e60

#define GPR0	ITCN_BASE + 0x0
#define GPR1	ITCN_BASE + 0x1
#define GPR2	ITCN_BASE + 0x2
#define GPR3	ITCN_BASE + 0x3
#define GPR4	ITCN_BASE + 0x4
#define GPR5	ITCN_BASE + 0x5
#define GPR6	ITCN_BASE + 0x6
#define GPR7	ITCN_BASE + 0x7
#define GPR8	ITCN_BASE + 0x8
#define GPR9	ITCN_BASE + 0x9
#define GPR10	ITCN_BASE + 0xa
#define GPR11	ITCN_BASE + 0xb
#define GPR12	ITCN_BASE + 0xc
#define GPR13	ITCN_BASE + 0xd
#define GPR14	ITCN_BASE + 0xe
#define GPR15	ITCN_BASE + 0xf
#define TIRQ0	ITCN_BASE + 0x10
#define TIRQ1	ITCN_BASE + 0x11
#define TIRQ2	ITCN_BASE + 0x12
#define TIRQ3	ITCN_BASE + 0x13
#define TISR0	ITCN_BASE + 0x18
#define TISR1	ITCN_BASE + 0x19
#define TISR2	ITCN_BASE + 0x1a
#define TISR3	ITCN_BASE + 0x1b
#define TCSR	ITCN_BASE + 0x1c


/* Analog-to-Digital Converter (ADC) */

#define ADCA_BASE	0x0e80

#define ADCA_ADCR1		ADCA_BASE + 0x0
#define ADCA_ADCR2		ADCA_BASE + 0x1
#define ADCA_ADZCC		ADCA_BASE + 0x2
#define ADCA_ADLST1		ADCA_BASE + 0x3
#define ADCA_ADLST2		ADCA_BASE + 0x4
#define ADCA_ADSDIS		ADCA_BASE + 0x5
#define ADCA_ADSTAT		ADCA_BASE + 0x6
#define ADCA_ADLSTAT	ADCA_BASE + 0x7
#define ADCA_ADZCSTAT	ADCA_BASE + 0x8
#define ADCA_ADRSLT0	ADCA_BASE + 0x9
#define ADCA_ADRSLT1	ADCA_BASE + 0xa
#define ADCA_ADRSLT2	ADCA_BASE + 0xb
#define ADCA_ADRSLT3	ADCA_BASE + 0xc
#define ADCA_ADRSLT4	ADCA_BASE + 0xd
#define ADCA_ADRSLT5	ADCA_BASE + 0xe
#define ADCA_ADRSLT6	ADCA_BASE + 0xf
#define ADCA_ADRSLT7	ADCA_BASE + 0x10
#define ADCA_ADDLLMT0	ADCA_BASE + 0x11
#define ADCA_ADDLLMT1	ADCA_BASE + 0x12
#define ADCA_ADDLLMT2	ADCA_BASE + 0x13
#define ADCA_ADDLLMT3	ADCA_BASE + 0x14
#define ADCA_ADDLLMT4	ADCA_BASE + 0x15
#define ADCA_ADDLLMT5	ADCA_BASE + 0x16
#define ADCA_ADDLLMT6	ADCA_BASE + 0x17
#define ADCA_ADDLLMT7	ADCA_BASE + 0x18
#define ADCA_ADHLMT0	ADCA_BASE + 0x19
#define ADCA_ADHLMT1	ADCA_BASE + 0x1a
#define ADCA_ADHLMT2	ADCA_BASE + 0x1b
#define ADCA_ADHLMT3	ADCA_BASE + 0x1c
#define ADCA_ADHLMT4	ADCA_BASE + 0x1d
#define ADCA_ADHLMT5	ADCA_BASE + 0x1e
#define ADCA_ADHLMT6	ADCA_BASE + 0x1f
#define ADCA_ADHLMT7	ADCA_BASE + 0x20
#define ADCA_ADOFS0		ADCA_BASE + 0x21
#define ADCA_ADOFS1		ADCA_BASE + 0x22
#define ADCA_ADOFS2		ADCA_BASE + 0x23
#define ADCA_ADOFS3		ADCA_BASE + 0x24
#define ADCA_ADOFS4		ADCA_BASE + 0x25
#define ADCA_ADOFS5		ADCA_BASE + 0x26
#define ADCA_ADOFS6		ADCA_BASE + 0x27
#define ADCA_ADOFS7		ADCA_BASE + 0x28

#define ADCB_BASE	0x0ec0

#define ADCB_ADCR1		ADCB_BASE + 0x0
#define ADCB_ADCR2		ADCB_BASE + 0x1
#define ADCB_ADZCC		ADCB_BASE + 0x2
#define ADCB_ADLST1		ADCB_BASE + 0x3
#define ADCB_ADLST2		ADCB_BASE + 0x4
#define ADCB_ADSDIS		ADCB_BASE + 0x5
#define ADCB_ADSTAT		ADCB_BASE + 0x6
#define ADCB_ADLSTAT	ADCB_BASE + 0x7
#define ADCB_ADZCSTAT	ADCB_BASE + 0x8
#define ADCB_ADRSLT0	ADCB_BASE + 0x9
#define ADCB_ADRSLT1	ADCB_BASE + 0xa
#define ADCB_ADRSLT2	ADCB_BASE + 0xb
#define ADCB_ADRSLT3	ADCB_BASE + 0xc
#define ADCB_ADRSLT4	ADCB_BASE + 0xd
#define ADCB_ADRSLT5	ADCB_BASE + 0xe
#define ADCB_ADRSLT6	ADCB_BASE + 0xf
#define ADCB_ADRSLT7	ADCB_BASE + 0x10
#define ADCB_ADDLLMT0	ADCB_BASE + 0x11
#define ADCB_ADDLLMT1	ADCB_BASE + 0x12
#define ADCB_ADDLLMT2	ADCB_BASE + 0x13
#define ADCB_ADDLLMT3	ADCB_BASE + 0x14
#define ADCB_ADDLLMT4	ADCB_BASE + 0x15
#define ADCB_ADDLLMT5	ADCB_BASE + 0x16
#define ADCB_ADDLLMT6	ADCB_BASE + 0x17
#define ADCB_ADDLLMT7	ADCB_BASE + 0x18
#define ADCB_ADHLMT0	ADCB_BASE + 0x19
#define ADCB_ADHLMT1	ADCB_BASE + 0x1a
#define ADCB_ADHLMT2	ADCB_BASE + 0x1b
#define ADCB_ADHLMT3	ADCB_BASE + 0x1c
#define ADCB_ADHLMT4	ADCB_BASE + 0x1d
#define ADCB_ADHLMT5	ADCB_BASE + 0x1e
#define ADCB_ADHLMT6	ADCB_BASE + 0x1f
#define ADCB_ADHLMT7	ADCB_BASE + 0x20
#define ADCB_ADOFS0		ADCB_BASE + 0x21
#define ADCB_ADOFS1		ADCB_BASE + 0x22
#define ADCB_ADOFS2		ADCB_BASE + 0x23
#define ADCB_ADOFS3		ADCB_BASE + 0x24
#define ADCB_ADOFS4		ADCB_BASE + 0x25
#define ADCB_ADOFS5		ADCB_BASE + 0x26
#define ADCB_ADOFS6		ADCB_BASE + 0x27
#define ADCB_ADOFS7		ADCB_BASE + 0x28


/* Serial Coummunications Interface (SCI) */
#define SCI0_BASE	0x0f00

#define SCI0_SCIBR	SCI0_BASE + 0
#define SCI0_SCICR	SCI0_BASE + 1
#define SCI0_SCISR	SCI0_BASE + 2
#define SCI0_SCIDR	SCI0_BASE + 3

#define SCI1_BASE	0x0f10

#define SCI1_SCIBR	SCI1_BASE + 0
#define SCI1_SCICR	SCI1_BASE + 1
#define SCI1_SCISR	SCI1_BASE + 2
#define SCI1_SCIDR	SCI1_BASE + 3


/* Serial Peripheral Interface (SPI) */
#define SPI_BASE	0x0f20

#define SPSCR	SPI_BASE + 0
#define SPDSR	SPI_BASE + 1
#define SPDRR	SPI_BASE + 2
#define SPDTR	SPI_BASE + 3


/* Computer Operating Properly */
#define COP_BASE	0x0f30

#define COPCTL	COP_BASE + 0
#define COPTO	COP_BASE + 1
#define COPSRV	COP_BASE + 2


/* Program Flash Interface Unit (PFIU) */
#define PFIU_BASE		0x0f40

#define PFIU_CNTL		PFIU_BASE + 0x0
#define PFIU_PE			PFIU_BASE + 0x1
#define PFIU_EE			PFIU_BASE + 0x2
#define PFIU_ADDR		PFIU_BASE + 0x3
#define PFIU_DATA		PFIU_BASE + 0x4
#define PFIU_IE			PFIU_BASE + 0x5
#define PFIU_IS			PFIU_BASE + 0x6
#define PFIU_IP			PFIU_BASE + 0x7
#define PFIU_CKDVISOR	PFIU_BASE + 0x8
#define PFIU_TERASEL	PFIU_BASE + 0x9
#define PFIU_TMEL		PFIU_BASE + 0xa
#define PFIU_TNVSL		PFIU_BASE + 0xb
#define PFIU_TPGSL		PFIU_BASE + 0xc
#define PFIU_TPROGL		PFIU_BASE + 0xd
#define PFIU_TVHL		PFIU_BASE + 0xe
#define PFIU_TVH1L		PFIU_BASE + 0xf
#define PFIU_TRCVL		PFIU_BASE + 0x10

/* Data Flash Interface Unit (DFIU) */
#define DFIU_BASE		0x0f60

#define DFIU_CNTL		DFIU_BASE + 0x0
#define DFIU_PE			DFIU_BASE + 0x1
#define DFIU_EE			DFIU_BASE + 0x2
#define DFIU_ADDR		DFIU_BASE + 0x3
#define DFIU_DATA		DFIU_BASE + 0x4
#define DFIU_IE			DFIU_BASE + 0x5
#define DFIU_IS			DFIU_BASE + 0x6
#define DFIU_IP			DFIU_BASE + 0x7
#define DFIU_CKDVISOR	DFIU_BASE + 0x8
#define DFIU_TERASEL	DFIU_BASE + 0x9
#define DFIU_TMEL		DFIU_BASE + 0xa
#define DFIU_TNVSL		DFIU_BASE + 0xb
#define DFIU_TPGSL		DFIU_BASE + 0xc
#define DFIU_TPROGL		DFIU_BASE + 0xd
#define DFIU_TVHL		DFIU_BASE + 0xe
#define DFIU_TVH1L		DFIU_BASE + 0xf
#define DFIU_TRCVL		DFIU_BASE + 0x10


/* Boot Flash Interface Unit (BFIU) */
#define BFIU_BASE		0x0f80

#define BFIU_CNTL		BFIU_BASE + 0x0
#define BFIU_PE			BFIU_BASE + 0x1
#define BFIU_EE			BFIU_BASE + 0x2
#define BFIU_ADDR		BFIU_BASE + 0x3
#define BFIU_DATA		BFIU_BASE + 0x4
#define BFIU_IE			BFIU_BASE + 0x5
#define BFIU_IS			BFIU_BASE + 0x6
#define BFIU_IP			BFIU_BASE + 0x7
#define BFIU_CKDVISOR	BFIU_BASE + 0x8
#define BFIU_TERASEL	BFIU_BASE + 0x9
#define BFIU_TMEL		BFIU_BASE + 0xa
#define BFIU_TNVSL		BFIU_BASE + 0xb
#define BFIU_TPGSL		BFIU_BASE + 0xc
#define BFIU_TPROGL		BFIU_BASE + 0xd
#define BFIU_TVHL		BFIU_BASE + 0xe
#define BFIU_TVH1L		BFIU_BASE + 0xf
#define BFIU_TRCVL		BFIU_BASE + 0x10


/* Clock Generation */
#define CLKGEN_BASE	0x0fa0

#define PLLCR		CLKGEN_BASE + 0
#define PLLDB		CLKGEN_BASE + 1
#define PLLSR		CLKGEN_BASE + 2
#define TESTR		CLKGEN_BASE + 3
#define CLKOSR		CLKGEN_BASE + 4
#define ISOCTL		CLKGEN_BASE + 5


/* General Purpose Input/Output (GPIO) */

#define GPIOA_BASE		0x0fb0

#define GPIO_A_PUR		GPIOA_BASE + 0x0
#define GPIO_A_DR		GPIOA_BASE + 0x1
#define GPIO_A_DDR		GPIOA_BASE + 0x2
#define GPIO_A_PER		GPIOA_BASE + 0x3
#define GPIO_A_IAR		GPIOA_BASE + 0x4
#define GPIO_A_IENR		GPIOA_BASE + 0x5
#define GPIO_A_IPOLR	GPIOA_BASE + 0x6
#define GPIO_A_IPR		GPIOA_BASE + 0x7
#define GPIO_A_IESR		GPIOA_BASE + 0x8


#define GPIOB_BASE		0x0fc0

#define GPIO_B_PUR		GPIOB_BASE + 0x0
#define GPIO_B_DR		GPIOB_BASE + 0x1
#define GPIO_B_DDR		GPIOB_BASE + 0x2
#define GPIO_B_PER		GPIOB_BASE + 0x3
#define GPIO_B_IAR		GPIOB_BASE + 0x4
#define GPIO_B_IENR		GPIOB_BASE + 0x5
#define GPIO_B_IPOLR	GPIOB_BASE + 0x6
#define GPIO_B_IPR		GPIOB_BASE + 0x7
#define GPIO_B_IESR		GPIOB_BASE + 0x8


#define GPIOD_BASE		0x0fe0

#define GPIO_D_PUR		GPIOD_BASE + 0x0
#define GPIO_D_DR		GPIOD_BASE + 0x1
#define GPIO_D_DDR		GPIOD_BASE + 0x2
#define GPIO_D_PER		GPIOD_BASE + 0x3
#define GPIO_D_IAR		GPIOD_BASE + 0x4
#define GPIO_D_IENR		GPIOD_BASE + 0x5
#define GPIO_D_IPOLR	GPIOD_BASE + 0x6
#define GPIO_D_IPR		GPIOD_BASE + 0x7
#define GPIO_D_IESR		GPIOD_BASE + 0x8


#define GPIOE_BASE		0x0ff0

#define GPIO_E_PUR		GPIOE_BASE + 0x0
#define GPIO_E_DR		GPIOE_BASE + 0x1
#define GPIO_E_DDR		GPIOE_BASE + 0x2
#define GPIO_E_PER		GPIOE_BASE + 0x3
#define GPIO_E_IAR		GPIOE_BASE + 0x4
#define GPIO_E_IENR		GPIOE_BASE + 0x5
#define GPIO_E_IPOLR	GPIOE_BASE + 0x6
#define GPIO_E_IPR		GPIOE_BASE + 0x7
#define GPIO_E_IESR		GPIOE_BASE + 0x8


#endif /* _56805_H */